1. Field of the Invention
The present invention relates to a semiconductor chip package and method for designing the same, and in particular to a semiconductor chip package with stagger vias and method for designing the same.
2. Description of the Related Art
FIG. 1 shows a cross section of a conventional semiconductor chip package 10. The semiconductor chip package 10 mainly comprises a package substrate 100 and a chip 106. The chip 106 is mounted on the top surface 102 of package substrate 100 and has a plurality of bonding pads 108 thereon. A plurality of fingers 112 and conductive traces 114, made of conductive material, are also formed on the top surface 102. By drilling through the package substrate 100 and filling conductive material therein, vias 116 are formed. Bonding wires 110, each having two ends disposed on one bonding pad 108 and one finger 112, electrically connects bonding pads 108 of the chip 106 to the fingers 112, to the conductive traces 114, and then to the vias 116. Ball pads 122 and conductive traces 124 are formed on the bottom surface 104. Attached on the ball pads 122 are solder balls 120. By way of solder ball conductance, ball pad 122, conductive traces 124, and chip 106 can electrically communicate with an external device. Each of the solder balls 120 are aligned at a distance away from any corresponding via 116, such that the package can be made by a cheaper manufacturing process. The conventional semiconductor chip package 10 may further comprise a top solder mask layer 101 on the top surface 102 and underlying the chip 106. The top solder mask layer 101 has openings to expose the fingers 112. The semiconductor chip package 10 may further comprise a bottom solder mask layer 105 on the bottom surface 104. The bottom solder mask layer 105 has openings to expose a portion of the ball pads 122, allowing solder balls 120 to be attached thereon.
As shown in FIG. 1, the vias 116 are located outside and far away from the zone where the corresponding ball pads 122 are. However, the ball pads and vias are closely placed in a finer ball pad pitch substrate due to the large number of balls required, it is difficult to place vias beside adjacent ball pads in a bonding fingers area as via-to-finger distance cannot be shorter than a predefined length. The finer ball pad pitch requirements thus force the vias to shift away from corresponding ball pads. The conductive trace connecting the vias and corresponding ball pads inevitably occupies certain routing space, which, if not occupied, may be utilized to route or form plating traces. The plating traces electrically connect all ball pads together before package substrate 100 is cut and singularized, allowing usage of a more economical electric-plating process. However, if not all ball pads and all fingers have corresponding plating traces, a higher-cost package substrate fabricating process, electroless plating or no plating line process is needed, thus increasing manufacture cost. Also, shifting vias far away may also result in longer conductive traces to the fingers or the ball pads, hindering electrical performances.